The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within semiconductor devices. As applications increasingly require higher performance related characteristics, semiconductor devices are continually redesigned to increase in precision and efficiency.
Device performance characteristics, and their relationship to semiconductor material properties and behaviors, are the subject of nearly constant scrutiny in a number of semiconductor production applications. One such application is the production and use of power transistors and high voltage devices. A number of such device rely on matching pairs of semiconductor structures—rendering the relationship between performance characteristics and material properties of great importance. As higher precision applications (e.g., sense transistors, precise ratio current mirrors) become more prevalent, there is a need for less variance in transistor performance parameters (e.g., gain factor (β), threshold voltage (VT)).
Typically, high voltage applications employ power transistors with a topologically closed loop 100 or “race track” geometry, as depicted in prior art FIG. 1. In racetrack geometries, the VT is typically lower in the end cap region 102 than in the straight regions 104. Racetrack geometries create double diffused regions (DWELL) 106 that diffuse outward from the straight or convex regions along its perimeter. As a result, end cap regions 102 turn “on” faster, creating performance anomalies within the transistor. Therefore, in applications or structures where parametric matching is critical, something must be done to deactivate or minimize the end cap region 102.
In a typical conventional device, region 106 may consist of Arsenic (As) and Boron (B) implants sufficiently diffused such that the Boron “outruns” Arsenic, forming a p-type channel, with As acting as a source extension. N-type source/drain implants 108 are self-aligned to the gate, making low-resistance electrical contacts. Because the geometries of such structures do not have uniform properties at all points along their perimeters, they may be conducive to varied two and three-dimensional diffusion effects.
In two-dimensional diffusions, dopants on straight region 104 diffuse from the As implanted region and diffuse laterally into the silicon. Its volume varies proportionally to diffused distance. On the curved section 102, however, the corresponding volume slice is a section of a spherical shell, and its volume varies as diffused distance squared. Thus, dopant concentration is diluted on convex regions 102 of the DWELL due to three-dimensional diffusion.
Three-dimensional doping effects also reduce dopant concentrations in curved regions 102. In order to illustrated the three dimensional diffusion effects on a concave mask geometry, consider dopant diffusion occurring from a concave DWELL region 200 such as depicted in FIG. 2.
As with the illustration of FIG. 1, region 200 has end cap regions 202 and straight regions 204. End cap regions 202 have a threshold voltage, VT, lower than that of the straight regions 204. As a result, end regions 202 “turn on” faster than the straight regions 204. Hence, curved end regions 202 dominate the device's performance properties. Thus, device width 206 directly influences a device's performance properties, such as VT.
Accordingly, a minimum-width DMOS device exhibits substantial reduction in the effective VT of the overall device. Large devices generally have fewer end caps 202 per unit perimeter and exhibit generally higher threshold voltages. Therefore, matching between a large DMOS device and a small DMOS device in, for example, a high-ratio current mirror circuit, can be adversely effected. Typically, conventional DMOS device geometries contain convex regions 202 that have a lower VT, degrading device precision.
Conventional end cap regions 202 may also be subject to different physical process-related distortions—such as oxide thinning, stress distribution, poly-channeling and auto-doping—due to their different proximities to field oxide regions.
As a result, there is a need for a system for producing high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices.